1. Field of the Invention
The present invention relates to a bus line wiring structure and a method of manufacturing the same that connects overlapping bus line layers with an intervening insulation layer between them, and more particularly, to a bus line wiring structure between a gate line and another line in a micro electrical device having a plurality of thin film transistors (TFTs) such as a liquid crystal display (LCD) device, a memory device, or a non-memory semiconductor device.
2. Discussion of the Related Art
In semiconductor fabrication, it is very important to maximize the number of TFTs that are integrated per unit area in a high density, micro-sized semiconductor device, such as a high resolution LCD device. In order to design a memory device having a higher capacitance or a higher resolution LCD device than an XGA (eXtended video Graphic Array) device, the number of TFTs per unit area must be increased. Thus, the bus lines connected with the TFTs are designed to be disposed in smaller spaces. Therefore, the space for connecting the gate line of the TFT and another line must be reduced.
The conventional method for connecting the bus lines formed in a separate layer to the wiring structure is shown in FIGS. 1a-2d. Specifically, FIG. 1a shows a cross sectional view of the connection for bus lines formed in a separate layer according to the conventional method, FIG. 1b shows the plan view of the wiring structure according to the conventional method, and FIGS. 2a-2d show the steps of the conventional manufacturing process.
As shown in FIG. 2a, a metal, such as aluminum or an aluminum alloy, is deposited on a substrate 11. The metal layer is patterned to form a low resistance gate line 15a. The surface of the low resistance gate line 15a is easily susceptible to hillock growth problem. The hillock growth is formed by being enlarged a grain of aluminum on the surface under high temperature during the following depositing processor such as an insulating layer depositing. The hillock of Al can be growing at 300xc2x0 C. or higher. Generally, the aluminum is deposited about 200xc2x0 C., so the hillock of Al can not be growing during the formation of the aluminum layer. However, the insulating layer is deposited at about 390xc2x0 C. So, when the insulating layer is deposited the hillocks of Al can be growing. A metal, such as chromium or molybdenum, is deposited on the substrate 11. The metal layer is patterned to form a gate line 15 covering the low resistance gate line 15a. The gate line 15 prevents the hillock problem from occurring in the low resistance gate line 15a. 
As shown in FIG. 2b, an insulation material such as silicon oxide or silicon nitride is deposited on the substrate having the gate line 15 to form a gate insulation layer 19. A metal, such as chromium or a chromium alloy, is deposited on the gate insulation layer 19. The metal layer is patterned to form a source line 35. The source line 35 is connected with the source electrode of the switching elements, such as a TFT.
As shown in FIG. 2c, an insulating material, such as a silicon nitride or a silicon oxide, is deposited on the substrate having the source line 35 to form a protection layer 39. The gate line 15 and the source line 35 are disposed on the separated layer with the intervening gate insulation layer 19 between them. Here, the gate line 15 and the source line 35 must not be connected to each other because they are used for different objects. However, they can be connected to each other as needed during some of the processing steps to protect them from static electricity. In addition, if a repair line for source line 35 is formed in the same layer and with the same material of the gate line 15, then the source line 35 should be connected to the repair line.
In order to connect the source line 35 and the gate line 15 (or the repair line in the same layer of the gate line 15), a gate contact hole 41 and a source contact hole 51 are formed, as shown in FIG. 2c. That is, at least a portion of a gate line 15 is exposed by etching the protection layer 39 and the gate insulation layer 19 to form the gate contact hole 41. Also, at least a portion of the source line 35 is exposed by etching the protection layer 39 to form the source contact hole.
As shown in FIG. 2d, a conductive material, such as an indium tin oxide (ITO), is deposited on the protection layer 39. The ITO layer is patterned to form a connecting terminal 53. The connecting terminal 53 connects the gate line 15 and the source line 35 through the gate contact hole 41 and the source contact hole 51.
In the conventional method for connecting the bus lines, the lines are connected by a third conductive material through the contact holes arrayed in horizontal. Hence, space is needed for the contact holes, thereby limiting the density of the semiconductor device. For example, in manufacturing a high density semiconductor device, all elements in the device are made smaller. Accordingly, the width of the gate line and the source line correspondingly becomes narrower. Furthermore, the number of connecting parts is increased, thereby hindering the reduction of the connection area.
Accordingly, the present invention is directed to a bus line wiring structure in a semiconductor device and method of manufacturing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide connection lines in a narrow space for the manufacturing of an electrical circuit board having multi-layered bus lines.
Another object of the present invention is to provide a simplified process for connecting lines formed in separate layers.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for manufacturing a wiring structure in a semiconductor device comprises the steps of forming a first conductive layer on a substrate; forming a second conductive layer covering a portion of the first conductive layer wherein another portion of the first conductive layer is not covered by the second conductive layer; forming an insulation layer on the first and the second conductive layers; and forming a third conductive layer connecting with the portion of the first conductive layer not covered by the second conductive layer.
In another aspect, the method for manufacturing a wiring structure in a semiconductor device comprises the steps of forming a first line and a connecting portion at an end portion of the first line; forming a second line covering the first line wherein at least a portion of the connecting portion is not covered by the second line; forming an insulation layer on the second line and the connecting portion; forming a penetrating part by growing a hillock through the insulation layer from the connecting portion; and forming a third line connecting with the penetrating part.
In another aspect, the wiring structure in a semiconductor device comprises a substrate; a first conductive layer on the substrate; a second conductive layer covering a portion of the first conductive layer, wherein another portion of the first conductive layer is not covered by the second conductive layer; an insulation layer on the first and second conductive layers; a penetrating part passing through the insulation layer from the uncovered portion of the first conductive layer; and a third conductive layer on the insulation layer, the third conductive layer connecting the penetrating part.
In another aspect, the wiring structure in a semiconductor device comprises a substrate; a first line on the substrate; a connecting portion at the end of the first line; a second line covering the first line; an insulation layer covering the second line and the connecting portion; a penetrating part passing through the insulation layer from the connecting portion; a third line on the insulation layer, the third line connecting the penetrating part.
In another aspect, the method for manufacturing a wiring structure in a semiconductor device comprises the steps of forming a line including an aluminum on a substrate; and forming a first metal layer covering the aluminum layer. Here, the portion of the aluminum layer which will be connected with another line is not covered by the first metal layer. The present invention further comprises the steps of an insulation layer on the aluminum layer and the first metal layer; and forming a second metal layer on the insulation layer with overlapping with the aluminum layer not covered by the first metal layer. Here, the aluminum layer not covered by the first metal layer has a hillock penetrating the insulation layer. Thus, the aluminum layer connects with the second metal layer through the hillock.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.